Reconfigurable architecture of RNS based high speed FIR filter

In this paper, a high speed reconfigurable FIR filter with multiple taps using accumulator based radix-4 multiplier is proposed. The 3n-bit binary input is converted into three residues using binary to residue number system (RNS) converter and then processed in three FIR sub filters constructed in direct form. The filter structure is implemented with a multiply and accumulate (MAC) architecture using accumulator based radix-4 multiplier. The reconfigurable structure is achieved by combining power of two (PoT) FIR sub modules and the coefficients are altered during runtime. The proposed design is tested and implemented for 20-tap FIR filter. The architecture is implemented using VHDL and synthesized using Altera cyclone II EP2C35F672C6. The performance results show that the architecture achieves low power and high speed and variable tap flexibility.